The present invention relates in general to semiconductor packaging and in particular to an apparatus and method of manufacture for a high performance flip chip package for semiconductor devices.
While silicon process technology has advanced significantly in the past decade, for the most part, the same decades-old package technology continues as the primary packaging means. Epoxy or solder die attach along with aluminum or gold wire bonding to lead frame is still the preferred semiconductor package methodology. Advances in semiconductor processing technology, however, have made the parasitics associated with conventional packages more of a performance limiting factor. This is particularly true in the case of power switching devices where, as in the case of power MOSFETs, the on-resistance of these devices continues to push the lower limits. Thus, the parasitic resistance introduced by the bond wires and the lead frame in conventional packages becomes much more significant for such high current devices as power MOSFETs. Furthermore, the continuous shrinking of geometries and the resulting increase in chip densities has given rise to an increasing demand for semiconductor packages with lead counts higher than that offered by the conventional packaging techniques.
Ball grid array and flip chip technologies were developed to address some of these demands. Both of these packaging technologies provide for a more direct connection between the silicon die and the printed circuit board as well as providing for higher interconnect densities. There is always room for improvement however. For example, a typical ball grid array package consists of a BT resin laminated board which serves as an interposer layer between the silicon die and the printed circuit board (PCB). Because of poor heat dissipation from the laminated board, external heat sinks and additional PCB copper layers are often required to dissipate excess heat.
In the case of conventional flip chip technology, among other shortcomings, heat dissipation is essentially governed by the die size and connection to the back side of the die is not easily facilitated (often requiring a bond wire connection). These limitations (poor heat dissipation and resistive contact to back side) become quite significant in high current applications such as power switching devices. A substantial improvement in the performance of flip chip packages is offered by Bencuya et al. in commonly assigned provisional Patent Application Ser. No. 60/088,651, (Attorney Docket No. 018865-0006) entitled "Low Resistance Package for Semiconductor Devices." In one embodiment, this improved package eliminates wire bonding by making direct connection between an array of solder balls on one conductive surface of the die and a lead frame element, while connection to the opposite side is made by a-die attached mechanism. This package exhibits significantly lower resistance; however, it still relies on a lead frame which adds residual resistance to the current path, and is not the smallest package possible for a given die size.
There is therefore a need for a high density semiconductor package whose attributes are minimal parasitic resistance and good heat dissipation, and that is readily manufacturable.